Cache Geometry Decides the Race

For years, Intel's Xeon line held an uncontested grip on server workloads. That grip loosened with the arrival of AMD's 2nd Gen EPYC processors (codenamed Rome), which introduced a very different cache topology built on the Zen 2 architecture. We took one of these Rome parts, the EPYC 7642, and ran it against our existing Intel hardware — both in a controlled lab environment and in live production traffic. The story that emerged is not about raw clock speed, but about where data lives when a core needs it.

The lab tests used a traffic pattern that mimics our production workloads: sustained HTTPS requests for cached 10 KiB PNG files. We tracked requests per second (RPS), instructions retired per second (IPS), sustained frequency, and L3 cache miss rate. Neither Intel Turbo Boost nor AMD Precision Boost was disabled, and we did not attempt to match frequencies between the platforms for this comparison.

Lab Results: A Clear Winner

The first thing that stands out is the cache hierarchy. A typical Cascade Lake Xeon shares roughly 1.375 MiB of L3 cache per core across the entire processor. The EPYC 7642 is different: each Core Complex (CCX) contains four cores and 16 MiB of L3 cache, and a Core Complex Die (CCD) pairs two CCXs. With eight CCDs, the 7642 presents a total of 256 MiB of L3 cache, or about 5.33 MiB per core.

In our simulated environment, a single-socket AMD EPYC 7642 server processed about 50% more requests per second than our dual-socket Intel Xeon Platinum 6162 server — a machine with the same total number of cores. Importantly, frequency alone does not explain that gap. The AMD processor ran at a sustained frequency roughly 20% higher than the Intel part. That would normally account for a modest performance edge, not a 50% RPS lead.

The missing piece is the L3 miss rate. With far more cache physically adjacent to each core, the AMD server retired substantially more instructions per second. Fewer trips to main memory meant more work completed per cycle, which is precisely what the higher instruction count reflects. This is the cache-locality effect in action: when working data stays on-die, the core stalls less and the system throughput climbs.

Real-World Validation

Encouraged by the lab numbers, we moved the AMD EPYC 7642-based server into a production point of presence alongside our Gen 7, Gen 8, and Gen 9 (Intel) machines. The production results were directionally consistent with the lab, though the margin narrowed. The AMD-powered server still outperformed every prior generation, including a 36% RPS improvement over the Intel Gen 9 baseline.

Two additional data points from production are worth noting. First, the sustained operating frequency was nearly identical to what we observed in the lab, confirming that the processor held its clock under real load. Second, the RPS gap was smaller than expected, which pulled down the instructions-retired metric and raised the L3 miss rate relative to the lab runs. The AMD machine still finished 29% ahead of Gen 9 on instructions retired, but the production environment is noisier: ambient temperature, traffic timing, and other system-level factors all play a role in any given data center region.

We collected data from a second PoP as well to make sure the first set of production numbers was not an anomaly. Both sites told the same story: the EPYC 7642 leads, but by a smaller margin in the field than in the lab.

Why the Cache Layout Matters

The shift to a chiplet design is not just a packaging choice — it changes how applications experience memory. In the Intel design, all cores contend for a single shared L3 pool. In the AMD Rome architecture, each CCX has its own dedicated slice of L3, which keeps frequently accessed data closer to the cores that use it. For workloads that fit within a 16 MiB CCX cache, the miss rate drops dramatically compared to a design where a distant, shared cache is the only option.

That geometry is the reason a single EPYC 7642 can outrun a dual-socket Xeon system with equivalent core counts. More data sits at cache latency instead of RAM latency, and the processor spends less time waiting on the memory bus. The result is a higher instruction retirement rate, which translates directly into more requests served per second.

Next Steps for the Fleet

The EPYC 7642 has opened a path for our next-generation servers to keep the same core count while handling more traffic per box. Our findings also give us a clearer picture of what to profile and measure in future hardware evaluations — the L3 miss rate is now a primary filter in our decision process. Still, our production observation came from a single PoP, and factors like thermal conditions and the introduction of new workloads (for example, WebAssembly on Cloudflare Workers) will shape traffic patterns going forward. The lab data is strong, but the full fleet-wide picture still needs time to develop.